2025 Talent Pipeline Full Custom Layout Engineer Jobs 聯發科技

2025 Talent Pipeline Full Custom Layout Engineer Jobs. 聯發科技 is offering vacancies for individuals with multiple skill sets and backgrounds. 聯發科技 is known for its dynamic work culture, competitive salaries, and sufficient oppportunities for growth. If you’re searching for a new job or to change your career, you might want to evaluate 聯發科技 as your upcoming step.

MediaTek’s Layout team is responsible to implement top quality layout of the integrated circuit for our chips. We are looking for result-driven candidates who can thrive under a fast-pace working environment and possess a strong desire to create an impact in the organization. Fresh graduates who are eager to get involved with industry most advanced semiconductor process technology are a perfect fit for our team. Candidates with strong passion in learning, problem solving, and decision-making skills are welcome to apply. Candidates will be able to develop in the following area: – Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow – Proficient in Synopsys/Cadence layout editor and physical verification tools; analytical and skillful in debugging DRC/LVS and all other verifications [What you will do] – Implement top quality layout which meet the specifications set forth by designers and layout leads while meeting the project objectives and fast paced milestones – Diligently perform all physical & reliability verifications (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow – Work closely and communicate effectively with multi-functional teams and multi-site to constantly optimize layout for better power, performance, area and schedule – Responsible for in-house IP/library developments

[Are you the right talent?] – Bachelor’s degree in Electrical/Electronic Engineering – Has transistor level knowledge for circuits and device layout structure – Understands analog layout fundamentals, such as floorplan, device matching, EM and IR – Have a good grasp of DRM of advanced node CMOS technologies – Team player and effective in cross-team communication and time management – Proficiency in script programming (e.g. Tcl, Perl or C-shell) is a plus

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